It is conventionally known that delay in a path of a circuit-under-design is calculated based on delay of cells making up the path, and that the delay of a cell is calculated based on conditions of process (P), temperature (P), and power voltage (V) (hereinafter “PTV condition”).
According to a conventionally known technique of calculating the delay of a cell, resistance and capacitance associated with a line connecting the cell to a cell immediately downstream are substituted by a single line capacitance value. Another conventionally known simulation technique involves simulation of an analog circuit by a simulator, such as SPICE, using a circuit model in which a line capacitance value and the input capacitance of a cell receiving output from the circuit are uniquely substituted by a load capacitance (lumped-constant capacitance value). According to yet another conventionally known simulation technique, the time required for a rise (or fall) in a waveform input to a cell (hereinafter “input-through time”) and a time required for a rise (or fall) in the waveform output from the cell (hereinafter “output-through time”) are included in the delay time of the cell (hereinafter “first conventional technique”) (see, e.g., Japanese Laid-Open Patent Publication Nos. H10-198720 and 2000-276501).
According to yet another conventionally known simulation technique, line resistance and line capacitance are extracted from layout data after layout design to carry out simulation based on an extraction result to improve the accuracy of the delay time (hereinafter “second conventional technique”) (see. e.g., Japanese Laid-Open Patent Publication No. H09-257880).
Although the waveform output from a cell is conventionally linear, a nonlinear output waveform, such as an output waveform having a stepped portion has been observed in recent years. The phenomenon of the nonlinear output waveform is caused by microprocessing and lower voltage. For example, (1) to (3) below are causes of such a phenomenon.
(1) Microprocessing reduces the thickness of the gate oxide film forming a transistor, thus leading to an increase in leak current. As a result, overshooting (or undershooting) occurs on the waveform output from a cell because of leak current from a cell immediately downstream or parasitic capacitance. In addition, the frequency and amplitude of wringing of the output waveform vary based on the gate size of the cell immediately downstream. (2) The ratio of vibration amplitude of wringing to the entire output waveform increases as operation voltage becomes lower. (3) The switching speed of a transistor drops in a type of cell having a low driving capability or under a PTV condition that lowers the driving capability, so that the maximum amplitude does not appear in wringing.
According to the first conventional technique, simulation is carried out using only the lumped-constant capacitance value. Consequently, multiple cells in the circuit-under-design each exhibit the same delay time even if the gate size of the respective cells immediately downstream differs with respect to one another. This poses a problem in that delay cannot be calculated respectively for each cell in the circuit-under-design. As a result, whether an output waveform is nonlinear cannot be reflected in the simulation, which leads to a problem of reduced accuracy of the estimated delay time.
According to the second conventional technique, a layout is designed without carrying out timing verification, and following the design layout, characteristics, such as line capacitance, are extracted from layout data to verify timing. This brings about a need for redesign of the layout. The characteristics are, therefore, extracted each time the layout is redesigned, making design troublesome and the convergence of timing impossible to cause estimation of the delay time of a cell to be difficult.